1. Field of the Invention
The present invention relates to disk drive performance features and more particularly to a disk drive having a cache control system for improving the disk drive""s response to host commands.
2. Description of the Prior Art
A host computer stores and accesses data on a disk drive by issuing commands to the disk drive over a standardized interface. The smallest indivisible data unit addressable on a disk is a logical block or disk sector, typically of 512 bytes, and each such disk sector is assigned a logical block address (LBA). When the host computer sends a command to the disk drive, the nature of the command is specified, e.g., read or write, along with a start LBA and a count specifying the number of contiguous sectors to be transferred.
Existing disk drives typically have a semiconductor cache memory for temporarily storing disk data that is likely to be requested by a host computer. The response time latency for storing and accessing data in a semiconductor memory is much smaller than the response time latency for mechanically storing and accessing data stored on a rotating disk. In existing disk drives, if an entire LBA range of a host command is not found, or if the first LBA of the host command is not buried within a segment or range of LBA""s stored in the cache memory, then a new cache segment is configured for responding to the host command. Accordingly, although the LBA range of the host command may overlap with the LBA range of a segment of the cache memory, that segment is essentially useless in responding to the host command.
Accordingly, there exists a need for a disk drive having a cache memory that may be configured to advantageously use existing cached data to respond to a host command. The present invention satisfies these needs.
The invention may be embodied in a disk drive, and related method, having a cache memory and a cache control system. The cache memory has a plurality of memory clusters for caching disk data of disk sectors identified by logical block addresses. The cache control system has a tag memory and a scan engine. The tag memory has a plurality of tag records. Each tag record defines a variable length segment of the memory clusters for caching disk data for a range of logical block addresses and indicates the range of logical block addresses. The scan engine is only usable for scanning the tag records. The scan engine includes means for receiving a range of logical block addresses associated with a host command, means for reading the ranges of logical block addresses defined by the tag records, means for comparing the range of logical block addresses associated with the host command with the ranges of logical block addresses indicated in the tag records, and means for providing scan results, based on a comparison by the means for comparing, indicating overlap between the logical block address range associated with the host command and the ranges of logical block addresses indicated in the tag records.
In a more detailed feature of the invention, the means for comparing may further determine whether a first logical block address of a range of logical block addresses associated with a host command is within the ranges of logical block addresses indicated in the tag memory records. The means for providing scan results may indicate the tag records, determined by the means for comparing, having a range including the first logical block address. The means for providing scan results may indicate whether an entire logical block address range, a portion of the logical block address range, or none of the logical block address range associated with a host command is within the ranges of logical block addresses in the tag memory records. The means for providing scan results also may indicate whether the logical block address range associated with a host command is buried within a range of the ranges of logical block addresses in the tag records or whether only a portion of the logical block address range associated with a host command is within a range of the ranges of logical block addresses in the tag memory records. Further, the means for providing scan results may indicate whether the portion includes the beginning or the end of the logical address range associated with the host command.
In another more detailed feature of the invention, the scan engine may accept a scan command, associated with a host command, from a microprocessor, a host writable control store and a host command decoder. The scan engine may include means for arbitrating between scan commands from the microprocessor, the host writable control store and the host command decoder.